Testing of Dynamic Logic Circuits Based on Charge Sharing

Dynamic logic is increasingly becoming a logic type of choice for designs requiring high speed and low area. Charge sharing is one of many problems that m a y cause failure in dynamic logic circuits due t o their low noise immunity . I n this paper, we address the charge sharing noise issue. Specifically, we develop an accurate but tractable model f o r analyzing charge sharing that avoids costly Hspice simulations. The model is used t o generate test vectors using a generalized ATPG tool. The charge-sharing model and the corresponding tests were validated using Hspice simulations on industrial circuits and it was also demonstrated that test vectors that establish high amounts of charge sharing could be generated for most domino gates.